The present invention relates to an A/D and D/A converter which is effectively utilized in A/D and D/A converters equipment employing, for instance, an oversampling type .DELTA.-.SIGMA. method.
In the oversampling .DELTA.-.SIGMA. type A/D and D/A converter as used in MODEMs and CODECs, input analog signals are sampled by oversampling clock signals whose frequency is an integral multiple of that of the sampling clock signal and are converted into digital signals which are then subjected to a specified weighting processing to extract output digital signals having an increased number of bits. The number of bits of the input digital signal synchronized with the sampling clock signal is compacted by an error integrating circuit to form a digital signal in synchronism with the oversampling clock signal, which digital signal is then converted into an output analog signal. In this way, a simple and high-performance A/D and D/A converter circuit is achieved. Such oversampling .DELTA.-.SIGMA. type A/D and D/A converters are introduced, for example, in the electrical communication engineers journal "Denki Tsushin Gakkai Shi", featuring the papers to be presented at the national congress of the electrical communication engineers association (communication field), No. 603,604.
FIG. 2 shows the block diagram of one example of the conventional oversampling .DELTA.-.SIGMA. type A/D converter ADE of this kind. The input analog signal Ain is applied to the A/D converter circuit of the A/D converter ADE where it is sampled according to the oversampling clock signal .phi.of. The oversampling signal .phi.of is supplied from a crystal oscillator in the converter and has a fixed frequency of 1.2288 MHz, for example. The A/D converter circuit A/D, in response to the oversampling clock signal .phi.of, samples the input analog signal Ain to transform the input signal into, for instance, an 8-bit digital signal d0-d7. The digital signal d0-d7 formed in each cycle of the oversampling clock signal .phi.of is weighted and decimated according to the sampling clock signal .phi.s1 by a decimator circuit DEC. The sampling clock signal .phi.s1 has a fixed frequency of 9.6 kHz, for example. The decimator circuit DEC, using 128 sets of digital signals d0-d7 corresponding to one cycle of the sampling clock signal .phi.s1, forms a 16-bit output digital signal D0-D15.
As the sampling clock signal .phi.s1 and the oversampling clock signal .phi.of both have fixed frequencies, the 128 sets of digital signals d0-d7 can always be related to one set of the output digital signal D0-D15. The decimating processing of the decimator circuit DEC is implemented by hardware formed according to the above architecture.
However, as shown in FIG. 2, when the output digital signal D0-D15 from the A/D converter ADE is supplied to the digital signal processor DSP for modulation or demodulation, the digital signal processor DSP extracts the sampling clock signal .phi.s1 from the input signal components. During the course of this processing, to adjust the synchronism between the sampling clock signal .phi.s1 and the input signal, it may become necessary to shift the phase (frequency) of the sampling clock signal .phi.s1.
As explained above, the decimating processing of the decimator circuit DEC requires that the frequency ratio of the sampling clock signal .phi.s1 and the oversampling clock signal .phi.of be in a stable relationship. Thus, if the digital signal d0-d7 goes out of phase with the output digital signal D0-D15 as a result of phase correction performed by the digital signal processor DSP, causing the number of oversamplings to change, the calculation for the weighting and decimating processing will not be carried out correctly. This in turn will deteriorate the S/N ratio of the MODE as a whole including the A/D converter ADE.
The objective of this invention is to provide oversampling type A/D and D/A converter with an enhanced operational stability and improved S/N ratio.
The above and other objectives and novel features of this invention, will become apparent from the following detailed description and attached drawings.
A typical example, of the invention disclosed in this application has a phase licked loop PLL circuit that synchronizes two signals--the oversampling clock signal supplied to the A/D converter circuit of the A/D and D/A converter using the oversampling method and the internal sampling clock signal supplied to the decimator circuit--with a sampling clock signal supplied from an external circuit.
With this means, since the sampling clock signal and the oversampling clock signal are synchronized in phase, the output digital signal from the A/D converter circuit, the output digital signal from the decimator circuit, and the data processing performed by the digital signal processor can all be synchronized, which contributes to improved stability of demodulation processing and a better S/N ratio of the MODEM equipment as a whole.